Priority is claimed to Japanese Patent Application Number JP2004-162654 filed on May 31, 2004, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a circuit device and a manufacturing method thereof, more particularly, to a circuit device including multilayered conductive patterns formed on a surface of a circuit substrate, and a manufacturing method thereof.
2. Description of the Related Art
A configuration of a conventional hybrid integrated circuit device will be described with reference to FIGS. 14A and 14B (this technology is described for instance in Japanese Patent Publication No. 6(1994)-177295 (p.4, FIG. 1)). FIG. 14A is a perspective view of hybrid integrated circuit device 100, and FIG. 14B is a cross-sectional view taken along the X–X′ line in FIG. 14A.
The conventional hybrid integrated circuit device 100 has a configuration as follows. The hybrid integrated circuit device 100 includes: a substrate 106 which is rectangular, an insulating layer 107 formed on a surface of the substrate 106; a conductive patterns 108 formed on this insulating layer 107; circuit elements 104 fixed onto the conductive patterns 108; metal thin wires 105 electrically connecting the circuit elements 104 to the conductive patterns 108; and leads 101 electrically connected to the conductive patterns 108. Moreover, the hybrid integrated circuit device 100 is entirely sealed by sealing resin 102.
Today, high-performance and high-output elements such as a system LSI are incorporated in hybrid integrated circuit devices. To incorporate such an element having numerous pins, it is necessary to form more complicated patterns inside a device and to ensure a high heat dissipation property. However, in the above-described hybrid integrated circuit device 100, it was difficult to cross wires because the conductive patterns 108 adopted a single-layer wiring structure. It is also possible to consider a configuration to use jumper wires in order to allow the conductive patterns 108 intersect. However, when the jumper wires are used, there is a risk that parasitic inductance occurs on locations of the jumper wires. Moreover, in consideration of the case where multilayered wiring is formed on the surface of the circuit substrate 106, there is also a problem of degradation in heat dissipation property of the entire device.
Meanwhile, in consideration of the case where a printed board including multilayered wiring is used as the circuit substrate 106, there is a problem that it is difficult to incorporate elements generating a high quantity of heat because the printed board has a poor heat dissipation property. Moreover, in consideration of the case of adopting a ceramic substrate, there is a problem of large wiring resistance.